In automotive electronics an increasing number of applications require large amounts of RAM (Random Access Memory), often many megabytes of RAM. The process technologies currently used limit the amount of RAM on chip for practical and economical reasons. A cost effective solution is to use standalone DRAM (Dynamic Random Access Memory) components. In particular, DRAM components used in Personal Computers (PCs) and mobile phones are readily available and cost competitive.
At the same time as memory capacity requirements are increasing, so is the need for increased functional safety. When the electronics module can brake and steer a vehicle without driver intervention, it needs to be ‘safe’. Functional safety requires that faults can be quickly and reliably detected. DRAM devices are prone to random changes to the data stored in the device. Functional safety requires that any change to the data in the DRAM device can be detected and, if possible, corrected.
Non-dynamic data in RAM devices which is constant and never expected to change (such as a code image) is simple to test for errors by periodically performing a cyclic redundancy check (CRC) or checksum of the constant data. However, dynamic data, which is constantly changed by the CPU or system, cannot be checked with a CRC or checksum.
A known solution for detecting errors in dynamic data in RAM devices is to perform a simple checksum of each data element (maybe 16 bits, 32 bits or 64 bits) and store the checksum in extra RAM bits associated with each data element. These checksum bits enable detection of an error and what the correct data should be. This is called ECC (Error Correction Coding) and is for instance applicable to correct single bit errors and detect double bit errors. For example, each 32-bit data element requires additionally 7 bits for the ECC checkbits.
US2012/0005559 A1 describes an apparatus and method for managing a DRAM buffer. The DRAM buffer managing apparatus may generate an error correction code (ECC) for data to be written in the DRAM buffer, and may write the data and the ECC bits in the DRAM buffer. An address translation table is used which indicates where in the DRAM buffer, the extra ECC bits are stored.